The present specification relates to the fabrication of integrated circuits (ICs). More specifically, the present specification relates to the thinning of trench, line spacing or contact spacing by use of a dual layer photoresist.
Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to put millions of devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC.
One limitation to the smallness of IC critical dimensions is conventional lithography. In general, projection lithography refers to processes for pattern transfer between various media. According to conventional projection lithography, a silicon slice, the wafer, is coated uniformly with a radiation-sensitive film or coating, the photoresist. An exposing source of radiation (such as light, x-rays, or an electron beam) illuminates selected areas of the surface through an intervening master template, the mask, for a particular pattern. The lithographic coating is generally a radiation-sensitive coating suitable for receiving a projected image of the subject pattern. Once the image is projected, it is indelibly formed in the coating. The projected image may be either a negative or a positive image of the subject pattern.
Exposure of the coating through a photomask or reticle causes the image area to become selectively crosslinked and consequently either more or less soluble (depending on the tone of the coating) in a particular solvent developer. The more soluble (i.e., uncrosslinked or deprotected) areas are removed in the developing process to leave the pattern image in the coating as less soluble polymer.
Projection lithography is a powerful and essential tool for microelectronics processing. As feature sizes are driven smaller and smaller, optical systems are approaching their limits caused by the wavelengths of the optical radiation.
One alternative to projection lithography is EUV lithography. EUV lithography reduces feature size of circuit elements by lithographically imaging them with radiation of a shorter wavelength. xe2x80x9cLongxe2x80x9d or xe2x80x9csoftxe2x80x9d x-rays (a.k.a, extreme ultraviolet (EUV)), wavelength range of lambda=50 to 700 angstroms are used in an effort to achieve smaller desired feature sizes.
In EUV lithography, EUV radiation can be projected onto a resonant-reflective reticle. The resonant-reflective reticle reflects a substantial portion of the EUV radiation which carries an IC pattern formed on the reticle to an all resonant-reflective imaging system (e.g., series of high precision mirrors). A demagnified image of the reticle pattern is projected onto a resist coated wafer. The entire reticle pattern is exposed onto the wafer by synchronously scanning the mask and the wafer (i.e., a step-and-scan exposure).
Although EUV lithography provides substantial advantages with respect to achieving high resolution patterning, errors may still result from the EUV lithography process. For instance, the reflective reticle employed in the EUV lithographic process is not completely reflective and consequently absorbs some of the EUV radiation. The absorbed EUV radiation results in heating of the reticle. As the reticle increases in temperature, mechanical distortion of the reticle may result due to thermal expansion of the reticle.
Both conventional projection and EUV lithographic processes are limited in their ability to print small features, such as, contacts, trenches, polysilicon lines or gate structures. As such, the critical dimensions of IC device features, and, thus, IC devices, are limited in how small they can be.
Integrated circuit (IC) fabrication techniques often utilize a photoresist material or layer to selectively form various IC structures, regions, and layers. Radiation is provided through or reflected off a mask or reticle to form an image on the photoresist layer on a semiconductor wafer. The photoresist layer is positioned to receive the radiation transmitted through or reflected off the mask or reticle. The image received by the photoresist layer corresponds to the pattern on the mask or reticle. The radiation can be light, such as ultra-violet light, vacuum ultra-violet (VUV) light and deep ultra violet light. The radiation can also be x-ray radiation, e-beam radiation, etc.
Generally, the patterned photoresist material can be utilized to define doping regions, deposition regions, etching regions, or other structures associated with an integrated circuit (IC). A conventional lithographic system is generally utilized to project the image to the photoresist material or layer. For example, conventional lithographic system includes a source of radiation, an optical system, and the reticle or photomask. The source of radiation provides radiation through the optical system and through or off of the mask or reticle. A pellicle can be employed between the mask and the wafer to protect the mask from acquiring particles on its surface which would cause defects to be printed.
According to one example of a conventional fabrication technique, light is exposed through a binary mask to a photoresist layer on a layer of material. The light can be provided at a number of different wavelengths including 248 nm, 193 nm, and 157 nm and EUV. The photoresist layer may be either a positive or a negative photoresist material.
In the case of a positive photoresist material, the light causes photochemical reaction in the photoresist layer. The photoresist layer is removable with a developer solution at the portions of the photoresist that are exposed to light through a mask. The photoresist layer is developed to clear away those portions. An integrated circuit feature, such as a gate, via, or interconnect, is then etched or doped into the layer of material, and the remaining photoresist is removed. In the case of a negative photoresist material, the light causes the photoresist layer to be removable with a developer solution at portions of the photoresist layer that are not exposed to light through the mask.
Various types of photoresist materials are manufactured by a number of manufacturers. The photoresist material can include multiple photoresist films (i.e. a multi-level resist (MLR)). According to some conventional processes, the photoresist layer is provided over an anti-reflective coating (ARC), such as silicon nitride (Si3N4) or silicon oxynitride (SiON). The anti-reflective coating is disposed above the material which is to be processed.
Conventional integrated circuit fabrication techniques may also include a process known as silylation. For example, U.S. Pat. No. 6,107,177 describes a silylation method for protecting resist and resist loss. Generally, silylation involves the introduction of a gas or a liquid containing silicon agents which react with silicon containing materials. Silicon containing agents include hexamethyl disilazane (HMDS), hexamethly-cyclotrisilazane, trimethylsilyl ethyl isocyanate and/or dimethysilyldimethylamine. Silicon containing agents may be supplied as a gas or a dry silylation method. Alternatively, silylation may be provided by employing a wet chemistry method. Often, dry chemistries can provide a more uniform and controlled silylation process. Heretofore, silylation has not been utilized to provide smaller critical feature dimensions for spaces by lateral swelling of sidewalls. Generally, silylation has been used as a hard mask on the top layer.
Thus, there is a need to pattern IC devices using non-conventional lithographic techniques. Further, there is a need to form smaller spacing feature sizes, such as, smaller contact holes and trench spaces. Yet further, there is a need to thin trench or contact spacing by using dual layer photoresist process.
An exemplary embodiment relates to a method of fabricating an integrated circuit. This method can include providing a bulk layer over a semiconductor substrate, providing an imaging layer over the bulk layer, imaging the imaging layer to expose portions of the imaging layer, removing the exposed portions of the imaging layer, etching the bulk layer at locations where exposed portions of the imaging layer were removed to provide at least one aperture in the bulk layer, and silylating the underlying bulk layer.
Another exemplary embodiment relates to a method of using a dual layer photoresist in fabricating an integrated circuit. This method can include providing a top layer and a bottom layer over a semiconductor substrate, patterning the top layer to remove portions of the top layer, etching the bottom layer to form spaces in areas of the bottom layer not covered by the top layer, and swelling the lateral sides of the spaces in the etched bottom layer in order to make spaces smaller than possible by lithography alone. The degree of swelling of the sidewalls and hence the amount of space narrowing achieved can be adjusted by duration of exposure to the silylation agent and varying the thickness of the bulk layer which is being silylated. In general, a thicker layer expands more making the space in the bulk layer narrower than when a thinner bulk layer is used.
Another exemplary embodiment relates to a method of forming narrow trenches or contact holes in a layer of photoresist. This method can include providing an imaging layer and a bulk layer, patterning narrow trenches or contact holes in the bulk layer by imaging the imaging layer and etching the bulk layer, and silylating lateral sidewalls of the patterned narrow trenches or contact holes in the bulk layer.
Other principle features and advantages of the present invention will become apparent to those skilled in the art upon review of the following drawings, the detailed description, and the appended claims.